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19-2713; Rev 1; 11/03
KIT ATION EVALU BLE AVAILA
12.5Gbps Settable Receive Equalizer
General Description Features
o Compensates Up to 30in (0.75m) of 6-mil FR-4 Transmission Line Loss o 115mW Operating Power o Up to 12.5Gbps Data Rate o Compatible with 8B10B, 64B66B, and PRBS Data o Less than 30psP-P Residual Jitter After Equalization o 3-Bit Equalization Level Select Input o 3mm x 3mm Thin QFN Package o DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O o -40C to +85C Operation o +3.3V Core Supply Voltage
MAX3804
The MAX3804 driver with integrated analog equalizer compensates up to 20dB of loss at 5GHz. It is designed to ensure PC board signal integrity up to 12.5Gbps, where frequency-dependent skin effect and dielectric losses typically produce unacceptable amounts of intersymbol interference. The MAX3804 can extend the practical chip-to-chip transmission distance for 10Gbps NRZ serial data up to 30in (0.75m) on FR-4, and it significantly decreases deterministic jitter. Residual jitter after equalization for 10.7Gbps signals is typically 24psP-P on the maximum path length. The MAX3804 is ideal for 10Gbps chip-to-chip serial interconnections on inexpensive FR-4 material. Its 3mm 3mm package affords optimal placement and routing flexibility. It has separate VCC connections for internal logic and current-mode logic (CML) I/O. This allows the CML input and output to be referenced to isolated supplies, providing independent DC-coupled interfacing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of input equalization can be selected through a digital control input, enabling the equalizer to be matched to a range of transmission line path loss. When correctly set to match the path loss, the MAX3804 provides optimal performance over a wide range of data rates and formats.
Ordering Information
PART MAX3804ETE TEMP RANGE -40C to +85C PINPACKAGE PACKAGE CODE
Applications
OC-192 and 10Gb Ethernet Switches and Routers OC-192 and 10Gb Ethernet Serial Modules High-Speed Signal Distribution
16 Thin QFN T1633F-3 (3mm x 3mm)
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
+1.8V +2.5V +3.3V VCC 10Gbps SERIAL OPTICAL MODULE SDO+ IN SDO+3.3V 30in OF FR-4 STRIPLINE OR MICROSTRIP TRANSMISSION LINE VCC VCC2 10Gbps SERDES SDI+ SDI-
VCC1
VCC MAX3804
SDI+ SDI-
SDO+ SDO-
EQ1 EQ2 EQ3 GND
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12.5Gbps Settable Receive Equalizer MAX3804
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ............................................-0.5V to +4.0V CML Supply Voltage (VCC1, VCC2) ............-0.5V to (VCC + 0.5V) Current at Serial Output (SDO+, SDO-) ............................25mA Input Voltage (SDI+, SDI-, EQ1, EQ2, EQ3) ..............................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 16-Lead Thin QFN-EP (derate 17.5mW/C above +85C) ........................................................1398mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, VCC1 = VCC2 = +1.65V to +3.6V, TA = -40C to +85C. Typical values are at VCC = VCC1 = VCC2 = +3.3V, and TA = +25C, unless otherwise noted.)
PARAMETER Supply Current CML Input Differential CML Input Common Mode CML Input Termination CML Input Return Loss CML Output Differential CML Output Impedance CML Output Transition Time Residual Jitter Output (Total RJ, PWD, and PDJ) LVTTL Input Current LVTTL Input Low LVTTL Input High IIH, IIL VIL VIH 2.0 tR, tF VOUT Single ended 20% to 80% (Notes 2, 6) At 10.7Gbps (Notes 3, 4, 5, 6) At 12.5Gbps (Notes 3, 4, 5, 6) -30 24 17 SYMBOL ICC VIN AC-coupled or DC-coupled (Note 1) DC-coupled Single ended Up to 5GHz 400 42.5 400 VCC1 - 0.4 42.5 50 10 500 50 600 57.5 35 30 30 +30 0.8 CONDITIONS MIN TYP 35 MAX 50 1200 VCC1 + 0.1 57.5 UNITS mA mVP-P V dB mVP-P ps psP-P A V V
Note 1: Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z0 = 100, 6-mil microstrip in FR-4, r = 4.5, and tan = 0.02, VIN = (SDI+ - SDI-). Note 2: Measured with 0000011111 pattern at 12.5Gbps. Note 3: Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmission line) and equalizer output. Total residual jitter is DJP-P + 14.2 x RJRMS. Note 4: Measured at 10.7Gbps using a pattern of 100 ones, 27PRBS, 100 zeros, 27PRBS, and at 12.5Gbps using a K28.5 pattern. Deterministic jitter at the input is from frequency-dependent, media-induced loss only. Note 5: VIN = 400mVP-P to 1200mVP-P, input path is 0 to 30in, 6-mil microstrip in FR-4, r = 4.5, and tan = 0.02. Note 6: Guaranteed by design and characterization.
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12.5Gbps Settable Receive Equalizer
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
RESIDUAL JITTER vs. INPUT AMPLITUDE
MAX3804 toc01 MAX3804 toc02
MAX3804
SUPPLY CURRENT vs. TEMPERATURE
85 VCC = VCC1 = VCC2 = 3.3V 70 SUPPLY CURRENT (mA) 35 30 RESIDUAL JITTER (psP-P) 25 20 15 10 5 10 -40 -15 10 35 60 85 TEMPERATURE (C) 0 400
RESIDUAL JITTER vs. FR-4 PATH LENGTH
400mVP-P INPUT AMPLITUDE 27PRBS WITH 100 CIDs AT 9.953Gbps
MAX3804 toc03 MAX3804 toc06
30in OF FR-4 TRANSMISSION LINE 27PRBS WITH 100 CIDs AT 9.953Gbps
35 30 RESIDUAL JITTER (psP-P) 25 20 15 10 5 0 3 9 15 K28.5 AT 12.5Gbps
55
40
K28.5 AT 12.5Gbps RESIDUAL JITTER = DJP-P + 14.2RJRMS 600 800 1000 1200 INPUT AMPLITUDE (mVP-P)
25 RESIDUAL JITTER = DJP-P + 14.2RJRMS 21 27 FR-4 PATH LENGTH (in)
RESIDUAL JITTER vs. EQUALIZATION SETTING
18in 31 RESIDUAL JITTER (psP-P) 24in 27 6in 23 30in RESIDUAL JITTER DJP-P + 14.2RJRMS
MAX3804 toc04
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc05
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4 (K28.5 AT 12.5Gbps)
35
60mV/ div
60mV/ div
19 3in 000 001 12in 010 011
15
400mVP-P, FR-4, 27 PRBS WITH 100 CIDs AT 10.7Gbps 100 101 110 111 16ps/div 16ps/div
EQUALIZATION SETTING (EQ3, EQ2, EQ1)
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12.5Gbps Settable Receive Equalizer MAX3804
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
EQUALIZER INPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc07
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc08
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (K28.5 AT 12.5Gbps)
MAX3804 toc09
60mV/ div
60mV/ div
60mV/ div
16ps/div
16ps/div
16ps/div
EQUALIZER OUTPUT EYE AFTER 24ft OF RG-188/U COAXIAL CABLE, SINGLE ENDED (27PRBS WITH 100 CIDs, 9.953Gbps)
MAX3804 toc10
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 3.2Gbps)
MAX3804 toc11
60mV/ div
60mV/ div
20ps/div
60ps/div
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12.5Gbps Settable Receive Equalizer
Pin Description
PIN 1, 4 2 3 5 6 7 8, 16 9, 12 10 11 13, 14 15 EP NAME VCC1 SDI+ SDIEQ1 EQ2 EQ3 GND VCC2 SDOSDO+ N.C. VCC Exposed Pad FUNCTION CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be AC-coupled. Positive Serial Data Input, CML Negative Serial Data Input, CML Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1. Equalizer Boost Control Logic Input, LVTTL. See Table 1. Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1. Supply Ground CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be AC-coupled. Negative Serial Data Output, CML Positive Serial Data Output, CML No Connection. Leave unconnected. +3.3V Core Supply Voltage Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance (see the Package and Layout Considerations section).
MAX3804
Detailed Description
General Theory of Operation
The MAX3804's low-noise linear input stage includes two amplifiers, one with flat-frequency response, and one with response that compensates for the loss characteristic of an FR-4 PC board transmission line. A current-steering network allows the designer to control the amount of equalization to match the path loss for specific applications. This network consists of a pair of variable attenuators feeding into a summing node. Equalization is set by a 3-bit LVTTL-compatible input (EQ3, EQ2, and EQ1). By employing fixed control of the equalization level, the MAX3804 provides optimal performance for a specific path loss. A high-speed limiting amplifier follows the equalizer circuitry to shape the output signal (see Figure 1).
CML Input and Output Buffers
The MAX3804 input and output CML buffers are terminated with 50 to VCC1 and VCC2, respectively. The equivalent circuit for the output is shown in Figure 2. Separate supply voltage connections are provided for the core (VCC), input (VCC1), and output (VCC2) circuitry to control noise coupling, and to allow DC-coupling to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs and outputs can also be AC-coupled. Use AC-coupling for single-ended cable applications. The unused CML input must be connected through an AC-coupling capacitor to a 50 termination. The low-frequency cutoff of the input-stage offset-cancellation circuit is nominally 21kHz.
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12.5Gbps Settable Receive Equalizer MAX3804
VCC1
VCC2
FLATRESPONSE AMPLIFIER 50 SDI+ CML SDIBOOSTRESPONSE AMPLIFIER 50
VARIABLE ATTENUATOR 50 50 SDO+ CML SDO-
VARIABLE ATTENUATOR
LIMITING AMP
MAX3804
EQ1 EQ2 EQ3 DIGITALTO-ANALOG CONVERTER
Figure 1. Functional Diagram
Applications Information
Equalizer Boost Level Control
The MAX3804 equalizer is intended for use at the receive end of an FR-4 PC board transmission line, typically up to 30in of differential 6-mil stripline or microstrip. It is specifically designed to mitigate intersymbol interference caused by the frequencydependent path loss of FR-4 transmission lines. It can also be used with a variety of other transmission-line materials and geometries, including coaxial cable, or PC board paths that include well-engineered connectors. Table 1 shows the relationship between nominal 6-mil FR-4 transmission line length and equalization setting.
VCC2 VCC
50
50 SDO+
MAX3804
ESD DIODES SDO-
Supply Voltage Connections
The CML input and output supplies (VCC1, VCC2) can be connected to +1.8V to +3.3V. VCC1 and VCC2 need not be connected to the same supply voltage; however, the core supply (VCC) must be connected to +3.3V.
Package and Layout Considerations
The MAX3804 is packaged in a 3mm x 3mm plasticencapsulated 16-lead thin QFN package. The package has an exposed pad that provides thermal and electrical connectivity to the IC and must be soldered to a high-frequency ground. Use good layout techniques for the SDI and SDO PC board transmission lines, and configure the trace geometry near the IC
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Figure 2. Simplified Output Structure
package to minimize impedance discontinuities. Power-supply decoupling capacitors should be as close as possible to the IC.
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12.5Gbps Settable Receive Equalizer
Table 1. Nominal 6-mil FR-4 Transmission Line Length and Equalization Settings
EQ3 0 0 0 0 1 1 1 1 EQ2 0 0 1 1 0 0 1 1 EQ1 0 1 0 1 0 1 0 1 NOMINAL 6-mil FR-4 MICROSTRIP LENGTH (in) 2 6 10 14 18 22 26 30
VCC1 SDI+ SDIVCC1 1 2 3 4 5 6 7 8
Pin Configuration
GND
MAX3804
N.C. 14
16
15
13 12 11
N.C.
VCC
VCC2 SDO+ SDOVCC2
MAX3804
10 9
Thin QFN* (3mm x 3mm)
*THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE.
Chip Information
TRANSISTOR COUNT: 1007 PROCESS: SiGe bipolar
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GND
EQ1
EQ2
EQ3
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12.5Gbps Settable Receive Equalizer MAX3804
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
REV.
D2 b
0.10 M C A B
D D/2
D2/2
E/2
E2/2
C L
-A-
E
(NE - 1) X e
E2
L
-B-
e
k (ND - 1) X e
C L
C L
0.10 C 0.08 C
C L
A A2 A1 L L
e
e
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO.
APPROVAL
21-0136
1 2
C
8
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12.5Gbps Settable Receive Equalizer
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3804
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
2 2
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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